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W948D6FB / W948D2FB
256Mb Mobile LPDDR
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification Parameters and Test Conditions
[Recommended Operating Conditions; Notes 1-3]
(256Mb, X16)
PARAMETER
Operating one
bank active-
precharge
current
SYMBOL
IDD0
TEST CONDITION
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH
between valid commands; address inputs are
SWITCHING; data bus inputs are STABLE
-5
40
-6
38
- 75
35
UNIT
mA
Precharge
power-down
standby current
Precharge
power-down
standby current
with clock stop
IDD2P
IDD2PS
all banks idle, CKE is LOW; CS is HIGH, tCK
= tCKmin ; address and control inputs are
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK =
LOW, CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
Low
power
Normal
power
Low
power
Normal
power
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
0.3
0.4
mA
mA
Precharge non
power-down
standby current
Precharge non
power-down
standby current
IDD2N
IDD2NS
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus
inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
10
3
10
3
10
3
mA
mA
with clock stop
SWITCHING; data bus inputs are STABLE
Active power-
down standby
current
Active power-
down standby
current with
IDD3P
IDD3PS
one bank active, CKE is LOW; CS is HIGH, tCK =
tCKmin;address and control inputs are SWITCHING; data
bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
3
3
3
3
3
3
mA
mA
clock stop
SWITCHING; data bus inputs are STABLE
Active non
power-down
standby current
Active non
power-down
standby current
IDD3N
IDD3NS
one bank active, CKE is HIGH; CS is HIGH, tCK =
tCKmin; address and control inputs are SWITCHING; data
bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, CK = LOW,
CK = HIGH; address and control inputs are
25
15
20
12
20
12
mA
mA
with clock stop
SWITCHING; data bus inputs are STABLE
Operating burst
read current
Operating burst
write current
Auto-Refresh
Current
Deep Power-
Down current
IDD4R
IDD4W
IDD5
IDD8(4)
one bank active; BL = 4; CL = 3; tCK = tCKmin ;
continuous read bursts; IOUT = 0 mA; address inputs are
SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change
each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is
HIGH; address and control inputs are SWITCHING; data
bus inputs are STABLE
Address and control inputs are STABLE; data bus inputs
are STABLE
75
55
50
10
70
50
50
10
70
50
50
10
mA
mA
mA
uA
Publication Release Date : Oct, 15, 2012
- 48 -
Revision : A01-004
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